1. Field of the Invention
The present invention relates to a method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell, and more particularly to a planarization of the bottom electrode top surface of a stack crown capacitor.
2. Description of the Prior Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the storage node of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs and capacitors have become continuously smaller so that the packing densities of these DRAM devices have increased considerably. For example, a number of semiconductor manufacturing companies in the world have already begun mass production of 64 Mbit DRAMs. These high density DRAMs offer the advantages of longer refresh time as well as less power consumption. However, as the sizes of the capacitors become smaller, so as the capacitance values of the capacitors are decreasing, that reduces the signal to noise ratio of the DRAM circuits, causing the performance problem. The issue of maintaining or even increasing the surface area of the storage nodes or reducing the thickness of the dielectric layer is particularly important as the density of the DRAM arrays continues to increase for future generations of memory devices.
There are two ways to deal with this problem: increasing the thickness of the bottom electrodes or increasing the surface area of the capacitors. Since increasing the thickness of the bottom electrodes is very difficult for precision lithography and etching control, increasing the capacitor surface area becomes an easier approach when the capacitor is used to fabricate 16 Mbit DRAMs and beyond. Various shapes of capacitor structures have been used to address this issue. U.S. Pat. No. 5,185,282 to Lee et al. of Hyundai Electronics (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating cup-shaped capacitor storage node. Another U.S. Pat. No. 5,021,357 to Taguchi et al. of Fujisu (the entire disclosure of which is herein incorporated by reference) discloses a method of fabricating fin structure capacitor electrode. U.S. Pat. No. 5,021,357 to Choi et al. of Samsung (the entire disclosure of which is herein incorporated by reference) provides a method of fabricating crown-shaped (or cylinder-shaped) capacitor structure.
Referring now to FIG. 1, there is shown a portion of partially completed Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). A dielectric layer 2 is deposited on a semiconductor substrate 1 which includes preformed electrical devices. Then, a contact window is opened in the dielectric layer 2 for forming a polysilicon plug 4. Next, a polysilicon bottom electrode 5 of a crown capacitor is formed by using conventional techniques of deposition, lithography and etching. There is a silicon nitride structure 3 as a bolster which can support the whole structure of the crown capacitor. Referring to FIG. 2, there is a cross-sectional view of the polysilicon surface corresponding to part A of FIG. 1, the step of etching makes the surface of the bottom electrode 5 rough. Therefore, a leakage current problem is induced by point discharge from the rough surface topology. In order to avoid this problem, the planarization of the bottom electrode 5 of the crown capacitor is usually achieved by the high-cost method of Chemical Mechanical Polishing (CMP), which increases the cost of DRAM process. Therefore, the present invention provides a new method of surface planarization for crown capacitor process to solve the above-mentioned problem.